1. Field of the Invention
The present invention relates to a method for accessing a memory having a cell array having a number of memory cells arranged in cell array elements. The invention furthermore relates to a memory in which such a method is carried out.
2. Description of the Related Art
Dynamic semiconductor memories, in particular DRAM (dynamic random access memory), have a memory cell array in which memory cells are interconnected with one another in matrix-type fashion in the form of rows and columns via word lines and bit lines. In this case, an individual memory cell of the memory cell array comprises a storage capacitor and a memory transistor, an information item (bit) being stored as electrical charge in the storage capacitor. The memory transistor, which is also referred to as selection transistor, serves as a switch in order to read or write an information item in the context of an access to a memory cell.
During a read access, a corresponding row or word line is activated by application of a row address to an activation apparatus of the memory. In this way, the memory transistors of memory cells of the relevant row are turned on, whereby the respective storage capacitors are connected to associated bit lines and the charges of the storage capacitors are thus added to the bit lines. The bit lines, which were precharged to an identical potential before the beginning of a read operation, are usually organized in pairs, in which case, through activation of a word line, a storage capacitor of a memory cell is in each case connected to one of the two lines of a bit line pair. In the case of a charged storage capacitor (logic 1 stored), the potential of a bit line is raised slightly, whereas an empty storage capacitor (logic 0 stored) slightly lowers the potential of a bit line. The second line of a bit line pair retains the respectively precharged potential.
In this way a charge difference arises between the bit lines of a bit line pair, which charge difference is amplified with the aid of a primary sense amplifier and subsequently made available to a secondary sense amplifier via switchable data line pairs. In this case, a plurality of primary sense amplifiers form a group and are connected to a secondary sense amplifier in each case via a switching device. Through application of a column address to a further activation apparatus of the memory, one of the switching devices and hence the relevant column is activated, whereby the datum read out by the respective primary sense amplifier is applied to the secondary sense amplifier. The datum present at the secondary sense amplifier can subsequently be output via corresponding data output lines.
The write operation differs only slightly from the read operation of a memory cell. In a corresponding manner, for the addressing of a memory cell, the relevant row or word line of the memory cell array is activated. The consequence of this is that once again a respective charge difference is brought about between the bit lines of bit line pairs which are connected to the enabled memory cells, said charge difference being amplified by primary sense amplifiers. Through activation of the relevant column, the datum to be written can subsequently be impressed on the selected memory cell with the aid of the secondary sense amplifier and the corresponding primary sense amplifier, in which case the signal to be written is not influenced by the existing weaker signal of the memory cell. The existing weaker signal of the memory cell is overwritten on account of the driver strength of the sense amplifiers used. The signal levels of the further bit line pairs are not influenced by the write operation, but rather are only amplified by the primary sense amplifiers as in the read operation.
Defects relating to individual memory cells or groups of memory cells occur virtually unavoidably in the production of DRAM memories. In order to increase the yield of usable memories after production, usually redundant memory cells are concomitantly processed in the memories in order to replace defective memory cells in the context of a memory access. In general, whole cell array elements, i.e. rows or columns which contain the affected defective memory cells, are directly replaced by redundant cell array elements.
For this purpose, the activation apparatuses provided in a memory are provided with programmable fusible links referred to as fuses. After a memory has been produced, functional tests are carried out on the memory with the aid of a test system in order to determine the addresses of defective cell array elements having defective memory cells. These addresses, referred to hereinafter as error addresses, are programmed into the fuses. So-called laser fuses are usually used, which can be severed in a corresponding laser trimming process with the aid of a laser beam for the purpose of storing the error addresses.
For the purpose of replacing defective memory cells in the context of a memory access, the address applied to an activation apparatus is compared with error addresses stored in the fuses. In the case of a match between the applied address and one of the error addresses, a defective row or a defective column is deactivated with the aid of the activation apparatus and a redundant row or column is activated instead of the relevant defective row or column.
In this context a problem can arise due to the fact that the activation of a cell array element by an activation apparatus in the case of an address applied to the activation apparatus can be carried out more rapidly than the comparison of the applied address with error addresses and deactivation of a defective cell array element. Particularly when a column is activated in the context of a read access, a risk thereby arises that a stored information item will be read out both from a defective column and from a redundant column and transmitted via corresponding data lines to a secondary sense amplifier and thus onto the data bus of the memory, whereby the read-out result is erroneous.
For this reason, the activation of a cell array element by an activation apparatus is delayed for a predetermined time duration starting from application of the corresponding address, in order to avoid access to a defective cell array element. However, a procedure of this type has a longer access time and thus results in an increased latency of the relevant memory.
Therefore, there is a need to provide a faster method for accessing a memory and also a memory having a shorter access time.